A majority of the portable multimedia embedded devices like mobile phone, notebook computers which interfaces with information from the real-world environment are essentially Digital Signal Processing (DSP) circuits whose main building block is a Multiplier-Accumulator (MAC). The performance of the full adders that are a part of the MAC unit can significantly affect the efficiency of the whole system. Hence the reduction of power consumption in Full adder circuit is necessary for low power applications. In this paper, the various adder cell circuits are implemented using different CMOS logic structures and their performance is analyzed in 130nm technology. Further, two novel Full adder cells called HYBRID I and HYBRID II are proposed for data path circuit and simulated using 130nm technology with BSIM model. The Post layout is developed for these adders and its Performances like Power, Delay and Power-delay product-PDP are analyzed and compared with the other existing adders. These Hybrid Full adders show the better performance than other adders and operate at low voltage with good signal integrity, thereby making them suitable for high performance applications.