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Feb 2024 - Volume 15, Issue 1
Deadline: 15 Jan 2024
Publication: 20 Feb 2024
Apr 2024 - Volume 15, Issue 2
Deadline: 15 Mar 2024
Publication: 20 Apr 2024
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ABSTRACT
Title |
: |
SPURIOUS POWER SUPPRESSION TECHNIQUE FOR VLSI ARCHITECTURE |
Authors |
: |
R.SESHADRI, G.HEMALATHA, V.VIJAYALAKSHMI |
Keywords |
: |
SPST,FIR,IIR,Power dissipation, Partial products. |
Issue Date |
: |
Dec 2012-Jan 2013 |
Abstract |
: |
Using spurious power suppression technique (SPST) in VLSI will reduce the power consumption of the system significantly. Here we are going to implement this design in Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filter architecture. When we are using this technique in this multipliers the no of partial products generated will be reduced to half which reduces the computation .Then obviously the power consumption is also reduced by this method using the Spartan 2 hardware device. |
Page(s) |
: |
746-750 |
ISSN |
: |
0976-5166 |
Source |
: |
Vol. 3, No.6 |
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