Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are a lack of design automation, a decreased tolerance to noise and increased power dissipation. In this work, new reduced – swing domino logic techniques which provide significant low power dissipation as compared to traditional domino circuit structures are proposed. The key idea of the new design styles is to limit both the upper and lower bounds of the voltage swing at the internal dynamic node. The voltage swing at the input and output of the circuits remains full – swing. The design styles are compared by performing detailed transistor level simulations on benchmark circuits such as OR2 gate, AND2 gate, XOR2 gate, 16-bit adder, 16-bit Comparator and 4-bit LFSR(Linear Feedback Shift Register) using Dsch3 and Microwind3 CAD tool.