e-ISSN:0976-5166
p-ISSN:2231-3850


INDIAN JOURNAL OF COMPUTER SCIENCE AND ENGINEERING

Call for Papers 2020

Jun 2020 - Volume 11, Issue 3
Deadline: 15 May 2020
Due to COVID-19 deadline extended to 31-May-2020
Notification: 15 Jun 2020
Publication: 30 Jun 2020

Aug 2020 - Volume 11, Issue 4
Deadline: 15 Jul 2020
Notification: 15 Aug 2020
Publication: 31 Aug 2020

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ABSTRACT

Title : LEAKAGE POWER OPTIMIZED SEQUENTIAL CIRCUITS FOR USE IN NANOSCALE VLSI SYSTEMS
Authors : M. Janaki Rani, Dr. S. Malarkkan
Keywords : Leakage power, pass transistors, process technology, stacking effect, transmission gates.
Issue Date : Feb-Mar 2012
Abstract :
As the density and operating speed of CMOS VLSI chips increases, leakage power dissipation becomes more and more significant. Therefore it is necessary to reduce the leakage power of portable battery operated devices. This paper proposes three power reduction techniques such as transistor stacking, self-adjustable voltage level circuit and reverse body bias for use in sequential circuits like D flip-flops and shift register. This work analyses the power of three different implementations of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. All the designs are simulated with and without the application of leakage reduction techniques and the readings are presented. Also two bit, four bit and eight bit shift registers are simulated with stack and reverse body bias leakage reduction techniques. The circuits are simulated with MOSFET models of level 54 using HSPICE in 65 nm process technology with a supply voltage of 1 volt. Simulation results show that the proposed pass transistor based D flip-flop circuit has the least leakage power dissipation. In the case of shift registers the combined stack and reverse body bias method gives minimum leakage power of 19.51nW, 32.16nW and 98.34nW for two bit, four bit and eight bit shift registers respectively.
Page(s) : 32-38
ISSN : 0976-5166
Source : Vol. 3, No.1