e-ISSN:0976-5166
p-ISSN:2231-3850


INDIAN JOURNAL OF COMPUTER SCIENCE AND ENGINEERING

Call for Papers

Apr 2019 - Volume 10, Issue 2
Deadline: 5 Apr 2019
Notification: 15 Apr 2019
Publication: 30 Apr 2019

June 2019 - Volume 10, Issue 3
Deadline: 5 June 2019
Notification: 15 June 2019
Publication: 30 June 2019

Indexed in

ABSTRACT

Title : SPURIOUS POWER SUPPRESSION TECHNIQUE FOR VLSI ARCHITECTURE
Authors : R.SESHADRI, G.HEMALATHA, V.VIJAYALAKSHMI
Keywords : SPST,FIR,IIR,Power dissipation, Partial products.
Issue Date : Dec 2012-Jan 2013
Abstract :
Using spurious power suppression technique (SPST) in VLSI will reduce the power consumption of the system significantly. Here we are going to implement this design in Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filter architecture. When we are using this technique in this multipliers the no of partial products generated will be reduced to half which reduces the computation .Then obviously the power consumption is also reduced by this method using the Spartan 2 hardware device.
Page(s) : 746-750
ISSN : 0976-5166
Source : Vol. 3, No.6