e-ISSN:0976-5166
p-ISSN:2231-3850


INDIAN JOURNAL OF COMPUTER SCIENCE AND ENGINEERING

Call for Papers

Apr 2019 - Volume 10, Issue 2
Deadline: 5 Apr 2019
Notification: 15 Apr 2019
Publication: 30 Apr 2019

June 2019 - Volume 10, Issue 3
Deadline: 5 June 2019
Notification: 15 June 2019
Publication: 30 June 2019

Indexed in

ABSTRACT

Title : PERFORMANCE EVALUATION OF AN EFFICIENT SINGLE EDGE TRIGGERED D FLIP FLOP BASED SHIFT REGISTERS USING CNTFET
Authors : Ravi.T, Kannan.V
Keywords : CNTFET, Single Edge Triggered D Flip Flop, power, Power Delay Product, Rise Time, Fall Time.
Issue Date : Aug-Sep 2013
Abstract :
Low power flip-flops are very important for low-power digital designs. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices have shrunk down to nanometer ranges. Due to the usage of millions of components and shrinking process technology, power consumption is drastically high in nano MOSFETs. Hence the paradigm has shifted to Carbon Nano Tube FET. In this paper, impact of 32nM MOSFET and 32nM CNTFET in the design of single edge triggered D-Flip Flop based shift registers are measured in terms of average power, delay, power delay product, rise time and fall time. MOSFET and CNTFET designs are simulated in 1GHz clock frequency and their performances are compared.
Page(s) : 272-279
ISSN : 0976-5166
Source : Vol. 4, No.4