Call for Papers

Apr 2019 - Volume 10, Issue 2
Deadline: 5 Apr 2019
Notification: 15 Apr 2019
Publication: 30 Apr 2019

June 2019 - Volume 10, Issue 3
Deadline: 5 June 2019
Notification: 15 June 2019
Publication: 30 June 2019

Indexed in


Title : Design of JK Flip-Flop using MODFET Technology
Authors : Ganesan.V, Shaji.K.S
Keywords : Flip-Flop, MODFET, delay, PDP, power consumption.
Issue Date : Dec 2013-Jan 2014
Abstract :
The pertinent choice of flip-flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance MODFET circuits. Understanding the suitability of flip-flops and selecting the best topology for a given application is an important issue to fulfill the need of the design to satisfy low power and high performance circuit. This paper enumerates high speed design of JK- flip-flop using AlGaAs/GaAs MODFET. The proposed Flip Flop is having less number of transistors than existing designs. Simulation results show lowest average power and least delay than existing designs. This Flip-Flop having less number of transistors. It can be efficiently used in VLSI ICs. In the verification by simulation, the proposed flip-flops appear to have better speed of operation. It is simple and suitable to SPICE simulation of hybrid digital ICs.
Page(s) : 474-480
ISSN : 0976-5166
Source : Vol. 4, No.6