e-ISSN:0976-5166
p-ISSN:2231-3850


INDIAN JOURNAL OF COMPUTER SCIENCE AND ENGINEERING

Call for Papers

Apr 2019 - Volume 10, Issue 2
Deadline: 5 Apr 2019
Notification: 15 Apr 2019
Publication: 30 Apr 2019

June 2019 - Volume 10, Issue 3
Deadline: 5 June 2019
Notification: 15 June 2019
Publication: 30 June 2019

Indexed in

ABSTRACT

Title : Comparison between simulations of different RBSD Adder Circuits
Authors : SOBINA GUJRAL, ROBINA GUJRAL
Keywords : RBSD adder, carry free addition,VHDL, high speed arithmetic.
Issue Date : Apr-May 2014
Abstract :
Adders are the key element of the arithmetic unit, especially fast parallel adder. Redundant Binary Signed Digit (RBSD) adders are designed to perform high-speed arithmetic operations. The RBSD Number System is gaining popularity due to the properties of carry-free addition / subtraction. In computational environment it is not convenient for manual computations but useful in designing high-speed arithmetic machines. This number system eliminates the carry / borrow propagation chains which reduces the computational time and enhances the speed of the machine. In this paper the circuit of fast RBSD adder cell proposed by Kal and Rajashekhar in 1990 and modified by N.Sharma in 2006, are designed using Hardware Discriptive Language and simulated on modelsim simulator.
Page(s) : 91-96
ISSN : 0976-5166
Source : Vol. 5, No.2