Adders are the key element of the arithmetic unit, especially fast parallel adder. Redundant Binary Signed Digit (RBSD) adders are designed to perform high-speed arithmetic operations. The RBSD Number System is gaining popularity due to the properties of carry-free addition / subtraction. In computational environment it is not convenient for manual computations but useful in designing high-speed arithmetic machines. This number system eliminates the carry / borrow propagation chains which reduces the computational time and enhances the speed of the machine. In this paper the circuit of fast RBSD adder cell proposed by Kal and Rajashekhar in 1990 and modified by N.Sharma in 2006, are designed using Hardware Discriptive Language and simulated on modelsim simulator.